Developments associated with encoding and decoding of digital data using an error-correcting code are being performed in the communications field, in the broadcasting field, and in the field of storages such as semiconductor memories.
Error-correcting codes can be broadly divided into codes to be subjected to algebraic hard-decision decoding and codes to be subjected to soft-decision decoding by iterative calculation based on probability.
In hard-decision decoding, when a threshold voltage corresponding to an amount of electric charge injected into a charge accumulation layer of a memory cell is applied to a word line, so-called hard bit data is read. However, memory cells have different threshold voltages even when the memory cells store same data, due to, e.g., manufacturing variations between the memory cells or conditions of the memory cells after charge accumulation. That is, threshold voltages for a plurality of memory cells storing the same data each have predetermined distributions. The reliability of data read at a voltage near a center of a peak of each threshold voltage distribution is high while the reliability of data read at a voltage near an upper limit or a lower limit of each threshold voltage distribution is low.
In soft-decision decoding, decoding is performed by iterative calculation using probability on a basis of soft bit read data read by applying intermediate voltages higher and lower than a hard bit read voltage.
Low density parity check codes (hereinafter referred to as “LDPC codes”) belonging to a group of codes to be subjected to soft-decision decoding are attracting attention. LDPC codes were first proposed by R. G. Gallager in 1963. After that, excellent performance approaching the Shannon limit that is a theoretical limit of code performance has been reported with an increase in a code length of an LDPC code.
For semiconductor memory devices having a NAND semiconductor memory section, storage of a plurality of bits of data in one memory cell, i.e., implementation of a so-called multi-level memory contributes largely to implementation of higher-density semiconductor memory devices.